1. Field of the Invention
The present invention relates to a semiconductor device wherein an n-channel MOSFET, a p-channel MOSFET and a nonvolatile memory cell are formed in one chip.
2. Description of the Related Art
An EPROM, which is an example of a nonvolatile semiconductor memory device, is made up mainly of a group of EPROM memory cells, and a peripheral circuit such as a decoder used for selecting the memory cells. In general, the peripheral circuit is constituted by a MOSFET. Presently-available MOSFETs include an n-channel MOSFET and a p-channel MOSFET, and an EPROM whose peripheral circuit is formed by using these two types of MOSFETs is generally referred to as a CMOS-type EPROM.
In the CMOS-type EPROM, an n-channel MOSFET and an n-channel EPROM memory cell are formed in the major surface of a p-type silicon substrate, and a p-channel type MOSFET is formed on the surface of an n-type well region provided in the p-type silicon substrate.
In the n-channel EPROM memory cell, hot electrons are generated in the channel region of the memory cell transistor, and data writing is carried out, with the hot electrons being captured in a floating gate. The hot electrons have to be implanted into each of a number of floating gates with no deviation. In other words, it is required that the electron concentrations in the floating gates be uniform. To meet with this requirement, the EPROM memory cells are formed on the substrate surface where the impurity concentrations are uniform and stable, and the entire memory cell region is applied with a uniform electric field. It should be noted that the impurity concentration in the substrate is determined in accordance with the characteristics of the EPROM memory cell.
In the circuit section formed by an n-channel MOSFET and a p-channel MOSFET, so-called latch-up becomes a problem. The latch-up is a phenomenon observed in the case where the n-channel MOSFET and the p-channel MOSFET are formed on the same substrate. In this case, a parasitic thyristor within the substrate may be turned on, resulting in a continuous current flow between the two MOSFETs. If the latch-up occurs, the circuit may become out of order; in some cases, it may be broken. If the n-channel MOSFET and the p-channel MOSFET are miniaturized, the latch-up becomes very likely to occur.
In the COMS-type EPROM, the impurity concentration in the substrate is increased, so as to prevent the latch-u between the n-channel MOSFET and the p-channel MOSFET.
In the above method for preventing latch-up, however, it is difficult to increase the impurity concentration in the substrate to an optimal degree, and the impurity concentration in the substrate is liable to become high. If the impurity concentration is too high, the EPROM memory cell may have different characteristics, for example, different writing speeds. If the two types of elements are further miniaturized, the latch-up becomes more likely to occur, so that the reliability of the device is degraded very much.